VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions1

Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the IEEE. VERIFY uses an integrated fault model, the dependability evaluation is very close to that of the actual hardware. Using simulation based fault injection, full observability and controllability of all components of the hardware is guaranteed. The impacts of faults have been investigated by several researchers. Several approaches towards this goal can be distinguished. Injecting faults at the physical level has been done by either stressing the hardware with environmental parameters or by modification of the pin-level values. The first method has been used by Karlsson et al. by inducing soft errors with heavy-ion radiation [15]. The second approach to inject faults at the physical level is the use of pin-level fault injectors, where the signal values of pins of an IC are under control of external devices which determine the time and duration of injection (MESSALINE [1] and RIFLE [19]). Whereas the latter method enables reproducibility of the results by the ability to control all fault parameters inducing soft errors corresponds more to the real physical nature of the faults. In addition, the current trend of integrating more and more components on-chip makes it difficult for pin-level fault injection to cover the internal faults adequately. Both approaches for the injection at the physical level tend to have a high overhead in hardware. Several research groups have developed powerful tools to inject faults by software. Barton et al. made one of the early approaches with a tool called FIAT [3], where the task's memory image can be corrupted during run-time. FERRARI, which was developed by Kanawati et al. [17] allows transient fault injection by corruption of a process's memory image and by insertion of software trap instructions. Kao et al. proposed a tool named FINE which is able to inject faults by using a software monitor to trace the control flow [16]. In addition, several examples for software implemented fault injection into existing systems Abstract A new technique for reliability evaluation of digital systems will be presented by demonstrating the functionality and usage of the simulation based fault injector VERIFY (VHDL-based Evaluation of Reliability by Injecting Faults efficientlY). This software tool …